@charset "UTF-8";
#DDR4 {
    background: url("../images/ddr4_1920.jpg") center no-repeat;
    height: 937px;
    padding-top: 170px;
}

#DDR4 .ddr4,
#DDR4 .pcie {
    width: 470px;
    margin: 0 auto;
}

#DDR4 .lgchart {
    margin-top: 50px;
}

#DDR4 .lgcharta {
    margin-top: 120px;
}

#DDR4 .schart {
    display: none;
}

@media screen and (max-width: 1366px) {
    #DDR4 {
        background-image: url(../images/ddr4_1366.jpg);
        height: 689px;
        padding-top: 150px;
    }
    #DDR4 .ddr4,
    #DDR4 .pcie {
        width: 400px;
    }
}

@media screen and (max-width: 960px) {
    #DDR4 {
        background-image: url("../images/ddr4_960.jpg");
        height: 1329px;
        padding-top: 130px;
    }
    #DDR4 .ddr4,
    #DDR4 .pcie {
        width: 372px;
    }
    #DDR4 .column+.column {
        margin-top: 160px;
    }
    #DDR4 .lgchart {
        margin-top: 30px;
    }
    #DDR4 .lgcharta {
        margin-top: 30px;
    }
}

@media screen and (max-width: 640px) {
    #DDR4 {
        background-image: url("../images/ddr4_640.jpg");
        height: 1436px;
    }
    #DDR4 .ddr4,
    #DDR4 .pcie {
        width: 100%;
    }
    #DDR4 .lgchart,
    #DDR4 .lgcharta {
        display: none;
    }
    #DDR4 .schart {
        display: block;
        margin-top: 40px;
    }
}